A dual in-line memory module (DIMM) usually includes a printed circuit board (PCB) and multiple memory chips distributed on the PCB, and the memory chip may be usually implemented by using a double data rate synchronous dynamic random-access memory (DDR SDRAM) that is most widely applied currently. The multiple memory chips are distributed on two sides of the PCB to form a symmetrical structure, memory chips on each side constitute an independent rank, and same pins in a same position of memory chips are connected to a same cable. Such a topology is referred to as a DDR dual-rank structure. The PCB in the DIMM is a multilayered structure.
Because the memory chips disposed on the two sides of the PCB have an exactly same structure, when the memory chips are symmetrically disposed, same pins of two memory chips may have different positions. Specifically, same pins of two memory chips are exactly symmetrically distributed about a midpoint of a line of centers of the two memory chips. In this case, a cable connected to same pins of two memory chips is usually designed as follows: A first cable section is disposed at a layer of the multilayered PCB board, one end of the first cable section is used as an input end, and the other end of the first cable section is connected to two pins by using a second cable section and a third cable section. Specifically, via holes separately facing the two sides of the PCB are disposed at the other end of the first cable section, and then the other end of the first cable section is connected to the two pins by using the second cable section and the third cable section, to form a T-type cable design. The other end of the first cable section is usually disposed close to one of the two pins. In this way, a relatively short second cable section connected to one pin may be ensured, and signal integrity (SI) of the pin is ensured. However, a relatively long third cable section connected to the other pin affects SI of the other pin. Consequently, overall performance of the DDR Dual Rank deteriorates. In addition, each cable may have a relatively long third cable section. Therefore, multiple layers need to be designed in a PCB to implement those cables, so as to prevent interference between the cables. Extremely high technological requirements are imposed on the PCB.